/*=============================================================================
# FileName    :	udp_user_tx.v
# Author      :	author
# Email       :	email@email.com
# Description :	
# Version     :	1.0
# LastChange  :	2018-08-27 13:50:30
# ChangeLog   :	
=============================================================================*/

`timescale  1 ns/1 ps

module udp_user_tx #
(
    parameter               TX_DATA_SIZE = 16'd284
)
(
    input   wire                clk,
    input   wire                rst,

    input   wire [31:00]        update_paramter,
    input   wire [07:00]        update_m_axi_tdata,
    input   wire                update_m_axi_tvalid,
    output  wire                update_m_axi_tready,
    input   wire                update_m_axi_tlast,

    input   wire [47:0]         rx_udp_srcmac,
    input   wire [31:0]         rx_udp_srcip,

    output  reg  [47:00]        m_axis_tdstmac,
    output  reg  [31:00]        m_axis_tdstip,
    output  wire [10:00]        m_axis_tlen,

    output  wire [07:00]        m_axis_tdata,
    output  wire                m_axis_tvalid,
    input   wire                m_axis_tready,
    output  wire                m_axis_tlast
);

always @(posedge clk)
begin
    m_axis_tdstmac  <= rx_udp_srcmac  ;
    m_axis_tdstip   <= rx_udp_srcip   ;
end

assign                  m_axis_tlen = TX_DATA_SIZE;

/*
 * 以下为测试代码
 */

assign                  m_axis_tdata = update_m_axi_tdata;
assign                  m_axis_tvalid = update_m_axi_tvalid;
assign                  m_axis_tlast = update_m_axi_tlast;
assign                  update_m_axi_tready = m_axis_tready;
endmodule
